The present invention relates to an apparatus and a method for controlling the sampling clock in a digital data transmission system. A synchronization word is transmitted at regular time intervals, by which the sampling clock at the receiving end is controlled. The received, sampled and filtered signal is supplied to a click control criterion filter and to an apparatus for identification of the synchronization word. The apparatus actuates a switch that supplies the clock control criterion to an adjustment logic device for the sampling clock (symbol clock).
The apparatus according to the invention and the method according to the invention are preferably intended for ISDN baseband subscriber connections.
In ISDN connection technology, baseband transmission methods (PAMP=pulse amplitude modulation, key word: 4B3T, 2R1Q) are used at the U-interface, with an unencrypted synchronization word being transmitted at regular time intervals for synchronization. The synchronization word is used to recover the frame structure (2xc3x97B+Exe2x80x94channels) once again at the receiving end. However, the control of the sampling clock at the receiving end can also be derived therefrom. The invention is based, as the prior art, on the present PRE 2091 and PRE 24911 (IRC-Q) U-module from the applicant.
The U-module provides clock control that derives the clock information from the received synchronization word.
It is accordingly an object of the invention to provide an apparatus and method for controlling the sampling clock in a data transmission system that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that further reduces the phase jitter on the symbol clock resulting from external and internal discrepancies and, at the same time, sets the symbol clock to the optimum sampling time in terms of achieving an error probability in response to random noise at the input that is as low as possible.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an apparatus for controlling a sampling clock in a digital data transmission system including a clock control criterion filter for filtering a received, sampled, and filtered signal, an adjustment logic device, a switch supplying a clock control criterion to the adjustment logic device for a sampling clock, an apparatus for identification of a synchronization word transmitted at regular time intervals and for receiving the received, sampled, and filtered signal, the apparatus programmed to actuate the switch for controlling the sampling clock at a receiving end of a digital data transmission system, a magnitude formation circuit, and a high-pass filter, the magnitude formation circuit and the high-pass filter disposed between the clock control criterion filter and the adjustment logic device.
The objectives of the invention are achieved in that, in the case of the apparatus according to the prior art, a magnitude formation circuit and a high-pass filter are disposed between the clock control criterion filter and the adjustment logic device for the symbol clock. Furthermore, according to the invention, the objectives are achieved by a method according to the prior art in which, in addition, the magnitude of the output value of the clock control criterion filter is formed, and is subjected to high-pass filtering before being supplied to the adjustment logic device.
With the objects of the invention in view, there is also provided a method for controlling a sampling clock in a digital data transmission system, including the steps of transmitting a synchronization word at regular time intervals, controlling a sampling clock at a receiving end of a digital data transmission system by the transmission of the synchronization word, filtering a received, sampled, and filtered signal with a clock control criterion filter and, at the same time, subjecting the received, sampled, and filtered signal to a detection method for identification of the synchronization word, controlling an adjustment logic device for a sampling clock on identification of a synchronization word with an output value of the clock control criterion filter, and forming a magnitude of the output value of the clock control criterion filter and subjecting the magnitude to high-pass filtering before supplying the magnitude to the adjustment logic device.
In accordance with another feature of the invention, it is particularly preferable for the transfer function of the high-pass filter or high-pass filtering to be (1xe2x88x92zxe2x88x921).
In accordance with a concomitant feature of the invention, (1xe2x88x92zxe2x88x921)5*(1xe2x88x92zxe2x88x922)*(1xe2x88x92k0, zxe2x88x921) is preferably chosen as the transfer function for the clock control criterion filter. It is particularly preferable to choose k0=xe2x88x92xe2x85x9c for short lines and k0=+xe2x85x9 for long lines. The definition of xe2x80x9cshortxe2x80x9d and xe2x80x9clongxe2x80x9d lines corresponds to the normal definition of these parameters in the prior art.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an apparatus and method for controlling the sampling clock in a data transmission system, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.